1. Field of the Invention
The present invention relates to circuitry for reducing noise (overshoot and undershoot) associated with the switching of electrical signals transmitted from one location to another. In particular, the present invention relates to an output buffer with control circuitry designed to regulate the potential at the control nodes of the buffer's output transistors.
2. Description of the Prior Art
Output buffers are used to transfer electrical signals of desired amplitude and strength. Signal transfers occur by way of buses--interfaces that couple active devices that are either on the same semiconductor-based chip or on different chips. The devices may be located proximate to one another, or they may be some distance from one another. One example of a proximate device interface requiring one or more bus connections is the coupling of one printed circuit board to another within a computing system, such as through a backplane bus. An example of a remote device interface requiring one or more bus connections is the coupling of one computing system to another, such as through a telephone transmission line that is, effectively, a voice/data bus.
Output buffers are used to ensure that electrical signals are transferred as accurately and as quickly as possible. It is often the case, however, that when transmission rates increase, signal accuracy may suffer. In particular, it is well known that rapid signal transmission may be accompanied by signal bounce. That is, the noise or ringing associated with the undershoot and overshoot of a final steady state logic high or logic low signal that occurs in the transition between high and low. The difference in the potentials associated with a high signal and a low signal may be as small as 0.4 V or as great as 5 V. For Complementary Metal Oxide Semiconductor (CMOS) based logic, for example, a logic high corresponds to a nominal 5.0 V potential (for a 5.0 V power supply) and a nominal 3.3 V potential (for a 3.3 V power supply), while a logic low is essentially equivalent to ground (GND) or 0.0 V.
The potentials associated with high and low signals described above are idealized values. In fact, highs and lows generally fall within a range of potentials associated with the indicated values. Thus, for a 3.3 V supply, a high signal may be supplied at 2.6 V, for example, while a low signal may actually be associated with a 0.7 V value. As the potentials of the power supplies used to power circuitry move closer to GND, the signal bounce mentioned above takes on greater importance. In particular, the initial oscillation around the ultimate steady state value that occurs when the transition between high and low is triggered may vary enough to generate a false logic signal. The noise swing may be enough to cause a low signal to transition to a high-signal potential and vice-versa, or it may be variable enough that the signal is not clearly at either a high potential or a low potential. Either situation is undesirable. For that reason, it is becoming increasingly important that the transitions between high and low signals occur with less noise than has been previously experienced.
Clearly, unexpected changes in logic values are not desirable. This problem is more likely to occur as transmission rates are increased. Increasing transmission rates enables the transfer of more data in a shorter time period and so is desirable in many respects. However, the gain in increased transmission rate is often undermined by an increase in signal noise. That is, a rapid change in signal level creates an oscillation about the steady state value corresponding to the sudden switching on or off of a transistor. As transistors become increasingly smaller in order to achieve the faster transmission rates of interest, the signal bounce that occurs with the rapid switching often creates reflections in transmission media, such as telephone transmission lines where reflections will cause signal errors. It is therefore important to enable "gentle" switching of buffer circuits so that signal noise is reduced.
A simplified illustration of a prior-art buffer circuit of the type that exhibits unacceptable signal bounce characteristics is presented in FIG. 1. The buffer circuit includes an input node input for receiving an electrical signal, and an output node output for the transfer of that signal to downstream circuitry. The input node is coupled to an inverter IV1 formed of P-type MOS transistor M1 and N-type MOS transistor M2. The output of the inverter IV1 is connected to the control node of pull-up P-type MOS transistor M3 and pull-down N-type MOS transistor M4. One and only one of transistors M3 and M4 is supposed to be turned on at a given time. When transistor M3 is on, the gate-source voltage (Vgs) exceeds the transistor's threshold voltage (Vt). The output node is at a logic high potential equivalent to high-potential power rail Vcc less the drain-source voltage (Vds) drop associated with transistor M3. In the case of MOS transistors, Vt is about 0.7 V. When transistor M4 is on, the output node is at a logic low potential equivalent to low-potential power rail GND. It can be seen that signal bounce at the control nodes of transistors M3 and M4 may create the situation where the wrong one may be on, they may be conducting simultaneously, or they may both be off. As indicated, any one of those conditions is undesirable.
Several attempts have been made to reduce the noise associated with a signal transition. U.S. Pat. No. 5,699,000 issued to Ishikuri describes a buffer circuit having means for regulating the voltage applied to the gates of the pull-up and pull-down transistors. This design affects transistor turn-on delay; however, it fails to solve overshoot and undershoot problems. U.S. Pat. No. 5,568,081 issued to Lui et al. describes a means for regulating the slew rate for the potential applied to the pull-up and pull-down transistors. The Lui buffer is quite complicated in that it utilizes a multitude of components. Such a complicated design makes it difficult to tune the turn-on of the output transistors. It also takes up more space on a chip than is otherwise desirable.
Therefore, what is needed is a buffer circuit that reduces the noise associated with signal switching without significantly compromising transmission rate. What is also needed is a buffer circuit that may be tuned to regulate the rate of turn-on of a pull-up or pull-down transistor. Further, what is needed is a "quiet" output buffer circuit that achieves the noted goals without complicated circuitry that takes up valuable layout space.